////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011-2012 Kentaro Sekimoto  All rights reserved.
////////////////////////////////////////////////////////////////////////////

#ifndef FM4_ANALOG_FUNCTIONS_H_
#define FM4_ANALOG_FUNCTIONS_H_

#include <tinyhal.h>

// ADCR : A/D Control Register
// ADSR : A/D Status Register
// SCCR : Scan Conversion Control Register
// SFNS : Scan Conversion FIFO Configuration Register
// SCFD : Scan Conversion FIFO Data Register
// SCIS : Scan Conversion Input Selection Register
// PCCR : Priority Conversion Control Register
// PFNS : Priority FIFO Number Selection Register
// PCFD : Priority Conversion FIFO Data Register
// PCIS : Priority Conversion Input Selection Register
// CMPD : A/D Comparison configuration register
// CMPCR: A/D Comparison Control Register
// ADSS : A/D Sampling time Selection register
// ADST : A/D Sampling Time configuration register
// ADCT : A/D Compare Time configuration register
// ADCEN: A/D Conversion Enable register

/*
 *  Register Bit Definition
 */
#define ADCR_OVRIE           0x01U
#define ADCR_CMPIE           0x02U
#define ADCR_PCIE            0x04U
#define ADCR_SCIE            0x08U
#define ADCR_CMPIF           0x20U
#define ADCR_PCIF            0x40U
#define ADCR_SCIF            0x80U
#define ADCR_IFALL           (ADCR_CMPIF | ADCR_PCIF | ADCR_SCIF)

#define ADSR_SCS             0x01U
#define ADSR_PCS             0x02U
#define ADSR_PCNS            0x04U
#define ADSR_FDAS            0x40U
#define ADSR_ADSTP           0x80U

#define SCCR_SSTR            0x01U
#define SCCR_SHEN            0x02U
#define SCCR_RPT             0x04U
#define SCCR_SFCLR           0x10U
#define SCCR_SOVR            0x20U
#define SCCR_SFUL            0x40U
#define SCCR_SEMP            0x80U
#define SCFDL_INVL           0x1000U

#define PCCR_PSTR            0x01U
#define PCCR_PHEN            0x02U
#define PCCR_PEEN            0x04U
#define PCCR_ESCE            0x08U
#define PCCR_PFCLR           0x10U
#define PCCR_POVR            0x20U
#define PCCR_PFUL            0x40U
#define PCCR_PEMP            0x80U
#define PCFDL_INVL           0x1000U

#define CMPCR_CMD0           0x20U
#define CMPCR_CMD1           0x40U
#define CMPCR_CMPEN          0x80U

#define ADCEN_ENBL           0x01U
#define ADCEN_READY          0x02U

struct FM4_AD_Driver
{
#if defined(MB9BF568R)
    static const UINT32 c_Channels = 24;
#else
#error "CPU type not defined. Please define MB9BF568R!"
#endif
    static const UINT8 c_Pins[c_Channels];
};

#endif /* FM4_ANALOG_FUNCTIONS_H_ */
